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LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 1 9/19/05 lds.3311-c video imaging products 111 mhz data rate 12-bit data and coeffcients on-board memory for 256 horizontal and 256 verti- cal coeffcient sets lf interface? allows all 512 coeffcient sets to be updated within vertical blanking selectable 12-bit data output with user-defned rounding and limiting seven 3k x 12-bit, programmable two-mode line buffers 16 horizontal filter taps 8 vertical filter taps two operating modes: dimensionally sepa- rate and orthogonal supports interleaved data streams horizontal filter supports decimation up to 16:1 for increasing number of filter taps 3.3 volt power supply 5 volt tolerant i/o 144 lead pqfp the LF3311 is an improved version of the lf3310 horizontal/vertical digital image filter capable of operating at speeds of up to 111mhz. this improved speed will increase fexibility and performance. the added performance will enable you to use this device in more applications. for example, four interleaved data streams of 27mhz can now be processed within one device. the part is functionally identical to the lf3310 with the exception that the flter data path is specifed to operate faster than the lf control interface. when operating the flter at speeds in excess of 90mhz, loading of coeffcients via the lf interface must be throttled to a maximum of 90mhz by asserting the pause pin as required to allow suffcient setup time for the confguration data provided to the figure 1 below demonstrates the switching waveforms of case 2, while the switching characteristics are shown in table 1. the LF3311 remains a two-dimensional digital image flter capable of fltering data at real-time video rates. the device contains both a horizontal and a vertical flter which may be cascaded or used concurrently for two-dimensional fltering. the input, coeffcient, and output data are all 12-bits and in twos complement format. the horizontal flter is designed to take advantage of symmetric coeffcient sets. when symmetric coeffcient sets are used, the horizontal flter can be confgured as a 16-tap fir flter. when asymmetric coeffcient sets are used, it can be confgured as an 8-tap fir f lter. the vertical flter is an 8-tap fir flter with all required line buffers contained on-chip. the line buffers can store video lines with lengths from 4 to 3076 pixels. horizontal flter interleave/decimation registers (i/d registers) and the vertical flter line buffers allow interleaved data to be fed directly into the device and fltered without separating the data into individual data streams. the horizontal flter can handle a maximum of sixteen data sets interleaved together. the vertical flter can handle interleaved video lines which contain 3076 or less data values. the i/d registers and horizontal accumulator facilitate using decimation to increase the number of flter taps in the horizontal flter. it will support a decimation factor of up to 16:1. the device has on-chip storage for 256 horizontal coeffcient sets and 256 vertical coeffcient sets. each flters coeffcients are loaded independently of each other allowing one flters coeffcients to be updated without affecting the other flters coeffcients. in addition, a horizontal or vertical coeffcient set can be updated independently from the other coeffcient sets in the same flter. features description figure 1. switching waveforms: lf interface tm devices incorporated ts 0 tc fs tpwh tc yc tp wl addr es s tp h pa us ea pa us eb cf a 11 -0 cf b 11- 0 tl h cl k ld a ld b tc fh tp s cf 0 cf 1
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 2 9/19/05 lds.3311-c video imaging products symbol parameter min max t cyc cycle time 9 t pwl clock pulse width low 4 t pwh clock pulse width high 4 t s0 input setup time 4 t s1 input setup time (xcen, xrsl) 4 t h0 input hold time 1 t h1 input hold time (xcen, xrsl) 1.5 t d output delay 8 t dis three-state output disable delay 10 t ena three-state output enable delay 10 t cfs coeffcient input setup time 5 t cfh coeffcient input hold time 1.5 t ls load setup time 4 t lh load hold time 1.5 t ps pause setup time 4 t ph pause hold time 1.5 table 1. switching characteristics commercial operating range (0oc to + 70oc) 9 (ns) speed grade figure 2. LF3311 block diagram di n 11-0 3k line buffe r 12 dout 11-0 12 256 coefficient set storage 256 coefficient set storage 16-tap horizontal filte r 8-tap vertical filte r 3k line buffe r 3k line buffe r 3k line buffe r 3k line buffe r 3k line buffe r 3k line buffe r devices incorporated
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 3 9/19/05 lds.3311-c video imaging products figure 3. LF3311 functional block diagram devices incorporated di n 11-0 3k line buffer c o c o dout 11-0 12 12 31 31 12 12 12 12 12 v coef bank 7 v coef bank 6 v coef bank 5 v coef bank 4 12 v coef bank 0 12 v coef bank 1 12 v coef bank 2 12 v coef bank 3 3k line buffer 3k line buffer 3k line buffer 3k line buffer 3k line buffer 3k line buffer 24 24 24 24 24 24 24 24 26 26 12 vca 7-0 vce n 8 12 12 12 12 12 12 12 12 rnd rnd vshe n "0 " vacc oe al u a b al u a b al u a b al u a b al u a b al u a b al u a b al u a b 13 h coef bank 0 12 h coef bank 1 12 h coef bank 2 12 h coef bank 3 12 13 13 13 13 13 13 13 h coef bank 7 12 h coef bank 6 12 h coef bank 5 12 h coef bank 4 12 25 25 25 25 25 25 25 25 27 27 hca 7-0 hce n 8 c o "0 " hacc 13 13 13 13 13 13 13 13 dat a dela y hshe n cl k cnf g 7-0 8 dat a dela y 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 limi t configuratio n register s cra 4-0 5 we i e o dat a reversal 1-16 lf hcf 11-0 hl d 12 lf vcf 11-0 vl d 12 txfr interface interface
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 4 9/19/05 lds.3311-c video imaging products the horizontal flter is designed to flter a digital image in the horizontal dimension. this fir flter can be confgured to have as many as 16-taps when symmetric coeffcient sets are used and 8-taps when asymmetric coeffcient sets are used. the alus double the number of flter taps available, when symmetric coeffcient sets are used, by pre- adding data values which are then multiplied by a common coeffcient (see figure 4). the alus can perform two operations: a+b and bCa. bit 0 of confguration register 0 determines the alu operation. a+b is used with even-symmetric coeffcient sets. bCa is used with odd-symmetric coeffcient sets. also, either the a or b operand may be set to 0. bits 1 and 2 of confguration register 0 control the alu inputs. a+0 or b+0 are used with asymmetric coeffcient sets. the interleave/decimation registers (i/d registers) feed the alu inputs. they allow the device to flter up to sixteen data sets interleaved into the same data stream without having to separate the data sets. the i/d registers should be set to a length equal to the number of data sets interleaved together. for example, if two data sets are interleaved together, the i/d registers should be set to a length of two. bits 1 through 4 of confguration register 1 determine the i/d register length. the i/d registers also facilitate using decimation to increase the number of flter taps. decimation by n is accomplished by reading the horizontal flters output once every n clock cycles. the device supports decimation up to 16:1. with no decimation, the maximum number of flter taps is sixteen. when decimating by n, the number of flter taps becomes 16n because there are nC1 clock cycles when the horizontal flters output is not being read. the extra clock cycles are used to calculate more flter taps. when decimating, the i/d registers should be set to a length equal to the decimation factor. for example, when performing a 4:1 decimation, the i/d registers should be set to a length of four. when not decimating or when only one data set (non-interleaved data) is fed into the device, the i/d registers should be set to a length of one. hshen enables or disables the loading of data into the forward and reverse i/d registers when the device is in dimensionally separate mode (see the hshen section for a full discussion). when in orthogonal mode, hshen also enables or disables the loading of data into the input register (din11-0) and the line buffers. it is important to note that in orthogonal mode, either hshen or vshen can disable the loading of data into the input register (din11-0), i/d registers, and line buffers. both must be active to enable data loading in orthogonal mode. functional description horizontal filter alu i/d registers figure 4. symmetric coeffcient set examples devices incorporated 1 2 3 4 5 6 7 8 even-tap, even-symmetri c coefficient se t odd-tap, even-symmetri c coefficient se t 1 2 3 4 5 6 7 8 even-tap, odd-symmetri c coefficient se t 1 2 3 4 5 6 7
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 5 9/19/05 lds.3311-c video imaging products the multiplexer in the middle of the i/d register data path controls how data is fed to the reverse data path. the forward data path contains the i/d registers in which data fows from left to right in the block diagram in figure 1. the reverse data path contains the i/d registers in which data fows from right to left. when the flter is confgured for an even number of taps, data from the last i/d register in the forward data path is fed into the frst i/d register in the reverse data path (see figure 5). when the flter is confgured for an odd number of taps, the data which will appear at the output of the last i/d register in the forward data path on the next clock cycle is fed into the frst i/d register in the reverse data path. bit 5 in confguration register 1 confgures the flter for an even or odd number of taps. when interleaved data is fed through the device and an even tap flter is desired, the flter should be confgured for an even number of taps (bit 5 of cr1 set to 0) and the i/d register length should match the number of data sets interleaved together. when interleaved data is to be fed through the device and an odd tap flter is desired, the flter should be set to odd-tap interleave mode. bit 0 of confguration register 1 confgures the flter for odd-tap interleave mode. when the flter is confgured for odd-tap interleave mode, data from the next to last i/d register in the forward data path is fed into the frst i/d register in the reverse data path. when the flter is confgured for an odd number of taps (interleaved or non-interleaved modes), the flter is structured such that the center data value is aligned simultaneously at the a and b inputs of the last alu in the forward data path. in order to achieve the correct result, the user must divide the coeffcient by two. data reversal circuitry is placed after the multiplexer which routes data from the forward data path to the reverse data path (see figure 6). when decimating, the data stream must be reversed in order for data to be properly aligned at the inputs of the alus. when data reversal is enabled, the circuitry uses a pair of lifos to reverse the order of the data sent to the reverse data path. when txfr goes low, the lifo sending data to the reverse data path becomes the lifo receiving data from the forward data path, and the lifo receiving data from the forward data path becomes the lifo sending data to the reverse data path. the device must see a high to low transition of txfr in order to switch lifos. if decimating by n, txfr should go low once every n clock cycles. when data reversal is disabled, the circuitry functions like an i/d register. when feeding interleaved data through the flter, data reversal should be disabled. bit 6 of confguration register 1 enables or disables data reversal. functional description figure 5. i/d register data paths i/d register data path control data reversal devices incorporated al u a b al u a b coef 7 coef 6 1-16 1-16 1-16 1-16 dat a reversal al u a b al u a b coef 7 coef 6 1-16 1-16 1-16 1-16 dat a reversal delay stage n 1 al u a b al u a b coef 6 1-16 1-16 1-16 1-16 dat a reversal even-tap mode odd-tap mode odd-tap interleave mode 2 coef 7 2 delay stage n
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 6 9/19/05 lds.3311-c video imaging products the horizontal flter output may be rounded by adding the contents of one of the sixteen horizontal round registers to the horizontal flter output wide output mode in the operating modes section). all programming of the device is done through the confguration registers via the 16-bit confguration/control interface. (see figure 7). each round register is 32-bits wide and user-programmable. this allows the flters output to be rounded to any precision required. since any 32-bit value may be programmed into the round registers, the device can support complex rounding algorithms as well as standard half-lsb rounding. hrsl3-0 determines which of the sixteen horizontal round registers are used in the rounding operation. a value of 0 on hrsl3-0 selects horizontal round register 0. a value of 1 selects horizontal round register 1 and so on. hrsl3-0 may be changed every clock cycle if desired. this allows the rounding algorithm to be changed every clock cycle. this is useful when fltering interleaved data. if rounding is not desired, a round register should be loaded with 0 and selected as the register used for rounding. round register loading is discussed in the lf interface? section. the word width of the horizontal flter output is 32-bits. however, only 12-bits may be sent to the flter output. the horizontal flter select circuitry determines which 12-bits are passed (see table 20). the horizontal select registers control the horizontal select circuitry. there are sixteen horizontal select registers. each select register is 5-bits wide and user-programmable. hrsl3-0 determines which of the sixteen horizontal select registers are used in the horizontal select circuitry. a value of 0 on hrsl3-0 selects horizontal select register 0. a value of 1 selects horizontal select register 1 and so on. hrsl3-0 may be changed every clock cycle if desired. this allows the 12-bit window to be changed every clock cycle. this is useful when fltering interleaved data. select register loading is discussed in the lf interface? section. an output limiting function is provided for the output of the horizontal flter. the horizontal limit registers determine the valid range of output values when limiting is enabled (bit 1 in confguration register 5). there are sixteen 24-bit horizontal limit registers. hrsl3-0 determines which horizontal limit register is used during the limit operation. a value of 0 on hrsl3-0 selects horizontal limit register 0. a value of 1 selects horizontal limit register 1 and so on. each limit register contains both an upper and lower limit value. if the value fed to the limiting circuitry is less than the lower limit, the lower limit value is passed as the flter output. if the value fed to the limiting circuitry is greater than the upper limit, the upper limit value is passed as the flter output. hrsl3-0 may be changed every clock cycle if desired. this allows the limit range to be changed every clock cycle. this is useful when fltering interleaved data. when loading limit values into the device, the upper limit must be greater than the lower limit. limit register loading is discussed in the lf interface? section. functional description figure 6. data reversal horizontal rounding horizontal select horizontal limiting 1-16 lifo a lifo b txfra/txfr b devices incorporated
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 7 9/19/05 lds.3311-c video imaging products functional description bits function description 0 alu mode 0 : a + b 1 : b C a 1 pass a 0 : alu input a = 0 1 : alu input a = forward register path 2 pass b 0 : alu input b = 0 1 : alu input b = reverse register path 11-3 reserved must be set to 0 table 2. confguration register 0 - address 200h figure 7. horizontal and verticle round/limit/select circuitry devices incorporated r0 r1 5 32 l0 l15 32 4 rs l 3- 0 rnd limi t 32 16 16 rsl circuitr y data in 32 data out s0 s15 5 selec t
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 8 9/19/05 lds.3311-c video imaging products the vertical flter is designed to flter a digital image in the vertical dimension. it is a fir flter which can be confgured to have as many as 8-taps. there are seven on-chip line buffers. the maximum delay length of each line buffer is 3076 cycles and the minimum is 4 cycles. confguration register 2 (cr2) determines the delay length of the line buffers. the line buffer length is equal to the value of cr2 plus 4. a value of 0 for cr2 sets the line buffer length to 4. a value of 3072 for cr2 sets the line buffer length to 3076. any values for cr2 greater than 3072 are not valid. the line buffers have two modes of operation: delay mode and recirculate mode. bit 0 of confguration register 3 determines which mode the line buffers are in. in delay mode, the data input to the line buffer is delayed by an amount determined by cr2. in recirculate mode, the output of the line buffer is routed back to the input of the line buffer allowing the line buffer contents to be read multiple times. bit 1 of confguration register 3 allows the line buffers to be loaded in parallel. when bit 1 is 1, the input register (din11-0) loads all seven line buffers in parallel. this allows all the line buffers to be preloaded with data in the amount of time it normally takes to load a single line buffer. vshen enables or disables the loading of data into the line buffers when the device is in dimensionally separate mode (see the vshen section for a full discussion). when in orthogonal mode, vshen also enables or disables the loading of data into the input register (din11-0) and the forward and reverse i/d it is important to note that in orthogonal mode, either hshen or vshen can disable the loading of data into the input register (din11-0), i/d registers, and line buffers. both must be active to enable data loading in orthogonal mode. the vertical flter is capable of handling interleaved data. the number of data sets it can handle is determined by the number of data values contained in a video line. if the interleaved video line has 3076 data values or less, the vertical flter can handle it no matter how many data sets are interleaved together. the vertical flter output may be rounded by adding the contents of one of the sixteen vertical round registers to the vertical flter output (see figure 7). each round register is 32-bits wide and user-programmable. this allows the flters output to be rounded to any precision required. since any 32-bit value may be programmed into the round registers, the device can support complex rounding algorithms as well as standard half-lsb rounding. vrsl3-0 determines which of the sixteen vertical round registers are used in the rounding operation. a value of 0 on vrsl3-0 selects vertical round register 0. a value of 1 selects vertical round register 1 and so on. vrsl3-0 may be changed every clock cycle if desired. this allows the rounding algorithm to be changed every clock cycle. this is useful when fltering interleaved data. if rounding is not desired, a round register should be loaded with 0 and selected as the register used for rounding. round register loading is discussed in the lf interface? section. the word width of the vertical flter output is 32-bits. however, only 12-bits may be sent to the flter output. the vertical flter select circuitry determines which 12-bits are passed (see table 20). the vertical select registers control the vertical select circuitry. there are sixteen vertical select registers. each select register is 5-bits wide and user-programmable. vrsl3-0 determines which of the sixteen vertical select registers are used in the vertical select circuitry. a value of 0 on vrsl3-0 selects vertical select register 0. a value of 1 selects vertical select register 1 and so on. vrsl3-0 may be changed every clock cycle if desired. this allows the 12-bit window to be changed every clock cycle. this is useful when fltering interleaved data. select register loading is discussed in the lf interface? section. vertical round- ing interleaved data vertical filter line buffers functional description vertical select devices incorporated
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 9 9/19/05 lds.3311-c video imaging products an output limiting function is provided for the output of the vertical flter. the vertical limit registers determine the valid range of output values when limiting is enabled (bit 0 in confguration register 5). there are sixteen 24-bit vertical limit registers. vrsl3-0 determines which vertical limit register is used during the limit operation. a value of 0 on vrsl3-0 selects vertical limit register 0. a value of 1 selects vertical limit register 1 and so on. each limit register contains both an upper and lower limit value. if the value fed to the limiting circuitry is less than the lower limit, the lower limit value is passed as the flter output. if the value fed to the limiting circuitry is greater than the upper limit, the upper limit value is passed as the flter output. vrsl3-0 may be changed every clock cycle if desired. this allows the limit range to be changed every clock cycle. this is useful when fltering interleaved data. when loading limit values into the device, the upper limit must be greater than the lower limit. limit register loading is discussed in the lf interface? section. vertical limiting functional description bits function description 11-0 line buffer length see line buffer description section table 4. confguration register 2 - address 202h bits function description 0 line buffer mode 0 : delay mode 1 : recirculate mode 1 line buffer load 0 : normal load 1 : parallel load 11-2 reserved must be set to 0 table 5. confguration register 3 - address 203h table 3. confguration register 1 - address 201h bits function description 0 odd-tap interleave mode 0 : odd-tap interleave mode disabled 1 : odd-tap interleave mode enabled 4-1 i/d register length 0000 : 1 register 0001 : 2 registers 0010 : 3 registers 0011 : 4 registers 0100 : 5 registers 0101 : 6 registers 0110 : 7 registers 0111 : 8 registers 1000 : 9 registers 1001 : 10 registers 1010 : 11 registers 1011 : 12 registers 1100 : 13 registers 1101 : 14 registers 1110 : 15 registers 1111 : 16 registers 5 horizontal tap number 0 : even number of taps 1 : odd number of taps 6 horizontal data reversal 0 : data reversal enabled 1 : data reversal disabled 11-7 reserved must be set to 0 devices incorporated
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 10 9/19/05 lds.3311-c video imaging products functiona l de scription bits function description 0 hv filter mode 0 : orthogonal mode 1 : dimensionally separate 1 hv direction 0 : horizontal to vertical 1 : vertical to horizontal 3-2 orthogonal kernel size 00 : 3-3 kernel 01 : 5-5 kernel 10 : 7-7 kernel 11 : not used 4 limit register load control 0 : limit registers always enabled 1 : limit registers under shift enable control 11-5 reserved must be set to 0 table 6. confguration register 4 - adress 204h bits function description 0 vertical limit enable 0 : vertical limiting disabled 1 : vertical limiting enabled 1 horizontal limit enable 0 : horizontal limiting disabled 1 : horizontal limiting enabled 11-2 reserved must be set to 0 table 7. confguration register 5 - adress 205h 11 10 9 description 0 0 0 coeffcient banks 0 0 1 confguration registers 0 1 0 horizontal select registers 0 1 1 vertical select registers 1 0 0 horizontal round registers 1 0 1 vertical round registers 1 1 0 horizontal limit registers 1 1 1 vertical limit registers table 8. hcf/vcf11-9 decode register address (hex) 0 400 1 401 14 40e 15 40f table 10 h select registers register address (hex) 0 c00 1 c01 14 c0e 15 c0f table 11 h limit registers register address (hex) 0 600 1 601 14 60e 15 60f table 13 v select registers register address (hex) 0 e00 1 e01 14 e0e 15 e0f table 14 v limit registers register address (hex) 0 a00 1 a01 14 a0e 15 a0f table 12 v round registers register address (hex) 0 800 1 801 14 80e 15 80f table 9 h round registers devices incorporated
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 11 9/19/05 lds.3311-c video imaging products the coeffcient banks store the coeffcients which feed into the multipliers in the horizontal and vertical flters. there is a separate bank for each multiplier. each bank can hold 256 12-bit coeffcients. the banks are loaded using an lf interface?. there is a separate lf interface? for the horizontal and vertical banks. coeffcient bank loading is discussed in the lf interface? section. the confguration registers determine how the hv filter operates. tables 2 through 7 show the formats of the six confguration registers. there are three types of control registers: round, select, and limit. there are sixteen round registers for the horizontal flter and sixteen for the vertical flter. each register is 32-bits wide. hrsl3-0 and vrsl3-0 determine which horizontal and vertical round registers respectively are used for rounding. there are sixteen select registers for the horizontal flter and sixteen for the vertical flter. each register is 5-bits wide. hrsl3-0 and vrsl3-0 determine which horizontal and vertical select registers respectively are used in the select circuitry. there are sixteen limit registers for the horizontal flter and sixteen for the vertical flter. each register is 24-bits wide and stores both an upper and lower limit value. the lower limit is stored in bits 11-0 and the upper limit is stored in bits 23-12. hrsl3-0 and vrsl3-0 determine which horizontal and vertical limit registers respectively are used for limiting when limiting is enabled. confguration and control register loading is discussed in the lf interface? section. functional description coeffcient banks confguration and control registers addr 1 coe f 0 coe f 7 addr 2 coe f 0 coe f 7 addr 3 coe f 0 coe f 7 coefficient set 1 coefficient set 2 coefficient set 3 cl k hld/vl d hcf/vcf 11-0 w1 w1: coefficient set 1 written to coefficient banks during this clock cycle. w2 w3 w2: coefficient set 2 written to coefficient banks during this clock cycle. w3: coefficient set 3 written to coefficient banks during this clock cycle. figure 8. coeffcient bank loading sequence addr 1 dat a 1 addr 3 dat a 4 config re g round register limit register cl k hld/vl d hcf/vcf 11-0 w2 w1: configuration register loaded with new data on this rising clock edge . w3 w4 w2: select register loaded with new data on this rising clock edge . w3: round register loaded with new data on this rising clock edge . dat a 1 dat a 3 dat a 2 addr 4 dat a 2 dat a 1 select re g addr 2 dat a 1 w4: limit register loaded with new data on this rising clock edge . w1 figure 9. confgurational/control register loading sequence devices incorporated
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 12 9/19/05 lds.3311-c video imaging products the horizontal and vertical lf interface? are used to load data into the horizontal and vertical coeffcient banks respectively. they are also used to load data into the confguration and control registers. the following section describes how the horizontal lf interface? works. the horizontal and vertical lf interface? are identical in function. if hld and hcf11-0 are replaced with vld and vcf11-0, the following section will describe how the vertical lf interface? works. hld is used to enable and disable the horizontal lf interface?. when hld goes low, the horizontal lf interface? is enabled for data input. the frst value fed into the interface on hcf11-0 is an address which determines what the interface is going to load. the three most signifcant bits (hcf11-9) determine if the lf interface? will load coeffcient banks or confguration/control registers (see table 8). the nine least signifcant bits (hcf8-0) are the address for whatever is to be loaded (see tables 9-14). for example, to load address 15 of the horizontal coeffcient banks, the frst data value into the lf interface? should be 00fh. to load horizontal limit register 10, the frst data value should be c0ah. the frst address value should be loaded into the interface on the same clock cycle that latches the high to low transition of hld (see figures 8 and 9). the next value(s) loaded into the interface are the data value(s) which will be stored in the bank or register defned by the address value. when loading coeffcient banks, the interface will expect eight values to be loaded into the device after the address value. the eight values are coeffcients 0 through 7. when loading select or confguration registers, the interface will expect one value after the address value. when loading round registers, the interface will expect four values after the address value. when loading limit registers, the interface will expect two values after the address value. figures 8 and 9 show the data loading sequences for the coeffcient banks and confguration/control registers. functional description lf interface ? figure 10. coeffcient bank loading sequence with hpause and vpause figure 11. confg and select register loading sequence with hpause and vpause addr 1 dat a 1 round register cl k w1 w1: round register loaded with new data on this rising clock edge . hpause/vpaus e dat a 2 dat a 3 dat a 4 hld/vl d hcf/vcf 11-0 addr 1 dat a 1 limit register cl k w1 w1: limit register loaded with new data on this rising clock edge. dat a 2 hld/vl d hcf/vcf 11-0 h pause/vpause devices incorporated
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 13 9/19/05 lds.3311-c video imaging products both hpause and vpause allow the user to effectively slow the rate of data loading through the lf interface?. when hpause is high, the lf interface? affecting the data used for the horizontal filter is held until hpause is returned to a low. when vpause is high, the lf interface? affecting the data used for the vertical filter is held until vpause is returned to a low. figures 10 through 13 display the effects of both hpause and vpause while loading coeffcient and control data. table 15 shows an example of loading data into the coeffcient banks. the following data values are written into address 10 of coeffcient banks 0 through 7: 210h, 543h, c76h, 9e3h, 701h, 832h, f20h, 143h. table 16 shows an example of loading data into a confguration register. data value 003h is written into confguration table 15 shows an example of loading data into the coeffcient banks. the following data values are written into address 10 of coeffcient banks 0 through 7: 210h, 543h, c76h, 9e3h, 701h, 832h, f20h, 143h. table 16 shows an example of loading data into a confguration register. data value 003h is written into confguration register 4. table 17 shows an example of loading data into a round register. data value 7683f4a2h is written into horizontal round register 12. table 18 shows an example of loading data into a select register. data value 00fh is loaded into horizontal select register 2. table 19 shows an example of loading data into vertical limit register 7. data value 390h is loaded as the lower limit and 743h is loaded as the upper limit. it takes 9s clock cycles to load s coeffcient sets into the device. therefore, it takes 2304 clock cycles to load all 256 coeffcient sets. assuming an 83 mhz clock rate, all 256 coeffcient sets can be updated in 28.8 s, which is well within vertical blanking time. it takes 5s or 3s clock cycles to load s round or limit registers respectively. therefore, it takes 256 clock cycles to update all round and limit registers (both horizontal and vertical). assuming an 83 mhz clock rate, all horizontal and vertical round/limit registers can be updated in 3.08 s. functional description lf interface ? continued figure 12. round register loading sequence with hpause and vpause figure 13. round register loading sequence with hpause and vpause devices incorporated addr 1 dat a 1 limit register cl k w1 w1: limit register loaded with new data on this rising clock edge . dat a 2 dat a 3 dat a 4 ld cf 11-0 paus e addr 1 dat a 1 round register cl k ld cf 11-0 w1 w1: round register loaded with new data on this rising clock edge . paus e dat a 2 dat a 3 dat a 4
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 14 9/19/05 lds.3311-c video imaging products the coeffcient banks and confguration/control registers are not loaded with data until all data values for the specifed address are loaded into the lf interfacetm. in other words, the coeffcient banks are not written to until all eight coeffcients have been loaded into the lf interfacetm. a round register is not written to until all four data values are loaded. after the last data value is loaded, the interface will expect a new address value on the next clock cycle. after the next address value is loaded, data loading will begin again as previously discussed. as long as data is loaded into the interface, hld must remain low. after all desired coeffcient banks and confguration/control registers are loaded with data, the lf interfacetm must be disabled. this is done by setting hld high on the clock cycle after the clock cycle which latches the last data value. it is important that the lf interfacetm remain disabled when not loading data into it. functional description cfa/b11 cfa/b10 cfa/b 9 cfa/b 8 cfa/b 7 cfa/b 6 cfa/b 5 cfa/b 4 cfa/b 3 cfa/b 2 cfa/b 1 cfa/b 0 1st word - address 1 0 0 0 0 0 0 0 1 1 0 0 2nd word - data r r r r 0 1 0 1 0 0 1 0 3rd word - data r r r r 1 1 1 1 0 1 0 0 4th word - data r r r r 1 0 0 0 0 0 1 1 5th word - data r r r r 0 ** 1 1 1 0 1 1 0 table 17. round register loading format cfa/b11 cfa/b10 cfa/b 9 cfa/b 8 cfa/b 7 cfa/b 6 cfa/b 5 cfa/b 4 cfa/b 3 cfa/b 2 cfa/b 1 cfa/b 0 1st word - address 0 1 0 0 0 0 0 0 0 0 1 0 2nd word - data 0 0 0 0 0 0 0 0 1 1 1 1 table 18. select register loading format h/vcf11 h/vcf10 h/vcf9 h/vcf8 h/vcf7 h/vcf6 h/vcf5 h/vcf4 h/vcf3 h/vcf2 h/vcf1 h/vcf0 1st word - address 1 1 1 0 0 0 0 0 0 1 1 1 2nd word - data 0* 0 1 1 1 0 0 1 0 0 0 0 3rd word - data 0** 1 1 1 0 1 0 0 0 0 1 1 table 19. limit register loading format lf interface ? continued cfa/b11 cfa/b10 cfa/b 9 cfa/b 8 cfa/b 7 cfa/b 6 cfa/b 5 cfa/b 4 cfa/b 3 cfa/b 2 cfa/b 1 cfa/b 0 1st word - address 0 0 1 0 0 0 0 0 0 1 0 0 2nd word - data 0 0 0 0 0 0 0 0 0 0 1 1 table 16. confguration register loading format h/vcf11 h/vcf10 h/vcf9 h/vcf8 h/vcf7 h/vcf6 h/vcf5 h/vcf4 h/vcf3 h/vcf2 h/vcf1 h/vcf0 1st word - address 0 0 0 0 0 0 0 0 1 0 1 0 2nd word - bank 0 0 0 1 0 0 0 0 1 0 0 0 0 3rd word - bank 1 0 1 0 1 0 1 0 0 0 0 1 1 4th word - bank 2 1 1 0 0 0 1 1 1 0 1 1 0 5th word - bank 3 1 0 0 1 1 1 1 0 0 0 1 1 6th word - bank 4 0 1 1 1 0 0 0 0 0 0 0 1 7th word - bank 5 1 0 0 0 0 0 1 1 0 0 1 0 8th word - bank 6 1 1 1 1 0 0 1 1 0 0 0 0 9th word - bank 7 0 0 0 1 0 1 0 0 0 0 1 1 table 15. coeffcient bank loading format * this bit represents the msb of the lower limit. ** this bit represents the msb of the upper limit. devices incorporated
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 15 9/19/05 lds.3311-c video imaging products the horizontal coeffcient banks may only be loaded with the horizontal lf interfacetm and the vertical coeffcient banks may only be loaded with the vertical lf interfacetm. the confguration and control registers may be loaded with either the horizontal or vertical lf interfacestm. since both lf interfacestm operate independently of each other, both lf interfacestm can load data into their respective coeffcient banks at the same time. or, one lf interfacetm can load the confguration/control registers while the other loads its respective coeffcient banks. if both lf interfacestm are used to load a confguration or control register at the same time, the vertical lf interfacetm will be given priority over the horizontal lf interfacetm. for example, if the horizontal lf interfacetm attempts to load data into a confguration register at the same time that the vertical lf interfacetm attempts to load a horizontal round register, the vertical lf interfacetm will be allowed to load the round register while the horizontal lf interfacetm will not be allowed to load the confguration register. however, the horizontal lf interfacetm will continue to function as if the write occurred. in dimensionally separate mode, the horizontal and vertical flters are cascaded together to form a two- dimensional image flter (see figures 14 and 15). bit 1 in confguration register 4 determines the cascade order. if this bit is set to 0, data on din11-0 is fed into the horizontal flter frst. the horizontal flter then feeds data into the vertical flter. if this bit is set to 1, data on din11-0 is fed into the vertical flter frst. the vertical flter then feeds data into the horizontal flter. dimensionally seperate mode operating modes figure 14. dimensionally seperate mode: h to v figure 15. dimensionally seperate mode: v to h lf interface ? continued functional description devices incorporated di n 11-0 horizontal filter vertical filter line buffer 12 line buffer line buffer line buffer line buffer line buffer line buffer dout 11-0 12 12 di n 11-0 horizontal filte r vertical filte r line buffe r 12 12 line buffe r line buffe r line buffe r line buffe r line buffe r line buffe r dout 11-0 12
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 16 9/19/05 lds.3311-c video imaging products in orthogonal mode, the horizontal and vertical flters are used concurrently to implement an orthogonal kernel on the input data (see figure 16). the hv filter can handle kernel sizes of 3-3, 5-5, and 7-7 (see figure 17). data delay elements at the input of the horizontal flter and the output of the vertical flter are used to properly align data so that the orthogonal kernel is implemented correctly. the data delays are automatically set to the correct lengths based on the programmed length of the line buffers and the kernel size. kernel sizes of 3-3, 5-5, and 7-7 require that the horizontal flters output be delayed by lb C 2, 2(lb) C 3, and 3(lb) C 4 clock cycles respectively before being added to the vertical flters output (lb is the programmed line buffer length). the data delay at the input of the horizontal flter handles the lb, 2(lb), and 3(lb) delays. the data delay at the output of the vertical flter handles the C 2, C 3, and C 4 delays. for example, if the line buffers are programmed for a length of 720 and a 5C5 kernel is selected, the horizontal flter input data delay will be 1440 clock cycles and the vertical flter output data delay will be 3 clock cycles. it is important to note that the frst 3, 5, or 7 multipliers of the horizontal and vertical flters must be used in orthogonal mode. if other multipliers are used, data from the horizontal and vertical flters will not line up correctly because the data delays are calculated assuming that the frst 3, 5, or 7 multipliers are used. also, the alus in the horizontal flter should be confgured to accept data from the forward i/d register path into alu input a and force alu input b to 0. operating modes figure 15. 3-3, 5-5, and 7-7 orthagonal kernels figure 14. orthogonal mode orthogonal mode v 2 v 3 hv 4 h 3 h 5 v 5 v 6 h 2 h 6 h 1 h 7 v 1 v 7 v 1 v 2 hv 3 h 2 h 4 v 4 v 5 h 1 h 5 v 1 hv 2 h 1 h 3 v 3 devices incorporated di n 11-0 horizontal filte r vertical filte r line buffe r 12 line buffe r line buffe r line buffe r line buffe r line buffe r line buffe r dout 11-0 12 dat a delay dat a delay
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 17 9/19/05 lds.3311-c video imaging products vcc and gnd +3.3 v power supply. all pins must be connected. clk master clock the rising edge of clk strobes all enabled registers. din 11-0 data input din 11-0 is the 12-bit data input port to filter a. in dual filter mode, din 11-0 can also be the 12-bit input port to filter b. data is latched on the rising edge of clock. hcf11-0 horizontal coeffcient input hcf11-0 is used to load data into the horizontal coeffcient banks and the confguration/control registers. data present on hcf11-0 is latched into the horizontal lf interface tm on the rising edge of clk when hld is low (see the lf interface tm section for a full discussion). hca7-0 horizontal coeffcient address hca7-0 determines which row of data in the horizontal coeffcient banks is fed to the multipliers in the horizontal flter. hca7-0 is latched into the horizontal coeffcient address register on the rising edge of clk when hcen is low. vcf11-0 vertical coeffcient input vcf11-0 is used to load data into the vertical coeffcient banks and the confguration/control registers. data present on vcf11-0 is latched into the vertical lf interface tm on the rising edge of clk when vld is low (see the lf interface tm section for a full discussion). vca7-0 vertical coeffcient address vca7-0 determines which row of data in the vertical coeffcient banks is fed to the multipliers in the vertical flter. vca7-0 is latched into the vertical coeffcient address register on the rising edge of clk when vcen is low. figure 16. input formats figure 17. accumulator output formats power signal defnitions clock inputs 31 30 29 2 1 0 2 20 (sign) 2 19 2 18 2 9 2 10 2 11 accumulator output devices incorporated 11 10 9 2 1 0 2 11 (sign) 2 10 2 9 2 2 2 1 2 0 11 10 9 2 1 0 2 0 (sign) 2 1 2 2 2 9 2 10 2 11 input data coefficient data
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 18 9/19/05 lds.3311-c video imaging products dout11-0 data output dout11-0 is the 12-bit registered data output port. hld horizontal coeffcient load when hld is low, data on hcf11-0 is latched into the horizontal lf interface tm on the rising edge of clk. when hld is high, data can not be latched into the horizontal lf interface tm . when enabling the lf interface tm for data input, a high to low transition of hld is required in order for the input circuitry to function properly. therefore, hld must be set high immediately after power up to ensure proper operation of the input circuitry (see the lf interface tm section for a full discussion). hcen horizontal coeffcient address enable when hcen is low, data on hca7-0 is latched into the horizontal coeffcient address register on the rising edge of clk. when hcen is high, data on hca7-0 is not latched and the registers contents will not be changed. vld vertical coeffcient load when vld is low, data on vcf11-0 is latched into the vertical lf interface tm on the rising edge of clk. when vld is high, data can not be latched into the vertical lf interface tm . when enabling the lf interface tm for data input, a high to low transition of vld is required in order for the input circuitry to function properly. therefore, vld must be set high immediately after power up to ensure proper operation of the input circuitry (see the lf interface tm section for a full discussion). vcen vertical coeffcient address enable when vcen is low, data on vca7-0 is latched into the vertical coeffcient address register on the rising edge of clk. when vcen is high, data on vca7-0 is not latched and the registers contents will not be changed. txfr horizontal filter lifo transfer control txfr is used to change which lifo in the data reversal circuitry sends data to the reverse data path and which lifo receives data from the forward data path. when txfr goes low, the lifo sending data to the reverse data path becomes the lifo receiving data from the forward data path, and the lifo receiving data from the forward data path becomes the lifo sending data to the reverse data path. the device must see a high to low transition of txfr in order to switch lifos. signal defnitions controls outputs table 20. output formats slct4-0 s15 s14 s13 s8 s7 s2 s1 s0 00000 f15 f14 f13 f8 f7 f2 f1 f0 00001 f16 f15 f14 f9 f8 f3 f2 f1 00010 f17 f16 f15 f10 f9 f4 f3 f2 01110 f29 f28 f27 f22 f21 f16 f15 f14 01111 f30 f29 f28 f23 f22 f17 f16 f15 10000 f31 f30 f29 f24 f23 f18 f17 f16 devices incorporated
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 19 9/19/05 lds.3311-c video imaging products hacc horizontal accumulator control when hacc is high, the horizontal accumulator is enabled for accumulation and the accumulator output register is disabled for loading. when hacc is low, no accumulation is performed and the accumulator output register is enabled for loading. hacc is latched on the rising edge of clk. vacc vertical accumulator control when vacc is high, the vertical accumulator is enabled for accumulation and the accumulator output register is disabled for loading. when vacc is low, no accumulation is performed and the accumulator output register is enabled for loading. vacc is latched on the rising edge of clk. hshen horizontal shift enable hshen enables or disables the loading of data into the forward and reverse i/d registers in the horizontal flter when the device is in dimensionally separate mode. if the device is confgured such that the horizontal flter feeds the vertical flter, hshen also enables or disables the loading of data into the input register (din11-0). if the device is confgured such that the vertical flter feeds the horizontal flter and the vertical limit register is under shift control, hshen also enables or disables the loading of data into the vertical limit register in the vertical round/select/limit circuitry. in orthogonal mode, hshen also enables or disables the loading of data into the input register (din11-0) and the line buffers in the vertical flter. it is important to note that in orthogonal mode, either hshen or vshen can disable data loading. both must be active to enable data loading in orthogonal mode. also in orthogonal mode, the horizontal and vertical limit registers can not be disabled. when hshen is low, data is loaded into and shifted through the registers hshen controls and the forward and reverse i/d registers on the rising edge of clk. when hshen is high, data is not loaded into or shifted through the registers hshen controls and the i/d registers, and their contents will not be changed. hshen is latched on the rising edge of clk. vshen vertical shift enable vshen enables or disables the loading of data into the line buffers in the vertical flter when the device is in dimensionally separate mode. if the device is confgured such that the vertical flter feeds the horizontal flter, vshen also enables or disables the loading of data into the input register (din11-0). if the device is confgured such that the horizontal flter feeds the vertical flter and the horizontal limit register is under shift control, vshen also enables or disables the loading of data into the horizontal limit register in the horizontal round/select/limit circuitry. in orthogonal mode, vshen also enables or disables the loading of data into the input register (din11-0) and the forward and reverse i/d registers in the horizontal flter. it is important to note that in orthogonal mode, either hshen or vshen can disable data loading. both must be active to enable data loading in orthogonal mode. also in orthogonal mode, the horizontal and vertical limit registers can not be disabled. when vshen is low, data is loaded into and shifted through the registers vshen controls and the line buffers on the rising edge of clk. when vshen is high, data is not loaded into or shifted through the registers vshen controls and the line buffers, and their contents will not be changed. vshen is latched on the rising edge of clk. signal defnitions controls contin- ued devices incorporated
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 20 9/19/05 lds.3311-c video imaging products hrsl3-0 horizontal round/select/limit control hrsl3-0 determines which of the sixteen user-programmable round/select/limit registers (rsl registers) are used in the horizontal round/select/limit circuitry (rsl circuitry). a value of 0 on hrsl3-0 selects rsl register 0. a value of 1 selects round/select/limit register 1 and so on. hrsl3-0 is latched on the rising edge of clk (see the horizontal round, select, andv limit sections for a complete discussion). vrsl3-0 vertical round/select/limit control vrsl3-0 determines which of the sixteen user-programmable rsl registers are used in the vertical rsl circuitry. a value of 0 on vrsl3-0 selects rsl register 0. a value of 1 selects rsl register 1 and so on. vrsl3-0 is latched on the rising edge of clk (see the vertical round, select, and limit sections for a complete discussion). oe output enable when oe is low, dout11-0 is enabled for output. when oe is high, dout11-0 is placed in a high-impedance state. hpause lf interfacetm pause when hpause is high, the horizontal lf interface tm loading sequence is halted until hpause is returned to a low state. this effectively allows the user to load coeffcients and control registers at a slower rate than the master clock (see the lf interface tm section for a full discussion). vpause lf interfacetm pause when vpause is high, the vertical lf interface tm loading sequence is halted until vpause is returned to a low state. this effectively allows the user to load coeffcients and control registers at a slower rate than the master clock (see the lf interface tm section for a full discussion). signal defnitions controls contd devices incorporated
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 21 9/19/05 lds.3311-c video imaging products operating conditions - to meet specifed electrical and switching characteristics mode temperature range (ambient) supply voltage active operation, commercial 0c to +70c 3.00 v < vcc o < 3.60 v active operation, military -55c to +125c 3.00 v < vcc o < 3.60 v specifcations maximum ratings - above which useful life may be impaired (notes 1,2,3,8) storage temperature .......................................................................................... C65c to +150c operating ambient temperature ......................................................................... C55c to +125c v cc o supply voltage with respect to ground ........................................................ C0.5 v to +4.5 v input signal with respect to ground ........................................................................ C0.5 v to 5.5 v signal applied to high impedance output ............................................................... C0.5 v to 5.5 v output current into low outputs ........................................................................................... 25 ma latchup current .............................................................................................................. > 400 ma esd classif cation (mil-std-883e method 3015.7) ..................................................... class 3 electrical characteristics - over operating conditions (note 4) symbol parameter test condition min typ max unit v oh output high voltage v cc = min., i oh = -4 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 v v ih input high voltage 2.0 5.5 v v il input low voltage (note 3) 0.0 0.8 v i ix input current ground < v in < v cc (note 12) + 10 a i oz output leakage current ground < v out < v cc (note 12) + 10 a i cc1 v cc current, dynamic (notes 5, 6) 250 ma i cc2 v cc current, quiescent (note 7) 2 ma c in input capacitance t a = 25c, f = 1 mhz 10 pf c out output capacitance t a = 25c, f = 1 mhz 10 pf switching waveforms: data i/o devices incorporated cl k di n 11-0 control s t pw t pw t cyc (except oe) oe dout 15-0 1 2 3 4 5 6 t h t s di n n di n n+1 t dd t dis high impedance t ena dout n - 1 7 dout n ca 7-0 ca n ca n+1 vb 11-0 vb n vb n+1 cout 11-0 high impedance cout n - 1 cout n t dc
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 22 9/19/05 lds.3311-c video imaging products 1. maximum ratings indicate stress specifcations only. functional operation of these products at values beyond those indicated in the operating conditions table is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. the products described by this specifcation include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. this device provides hard clamping of transient undershoot. input levels below ground will be clamped beginning at C0.6 v. the device can withstand indefnite operation with inputs or outputs in the range of C0.5v to +5.5v. device operation will not be adversely affected, however, input current levels will be well in excess of 100 ma. 4. actual test conditions may vary from those designated but operation is guaranteed as specifed. 5. supply current for a given application can be accurately approximated by: where 6. tested with outputs changing every cycle and no load, at a 40 mhz clock rate. 7. tested with all inputs within 0.1 v of v cc or ground, no load. 8. these parameters are guaranteed but not 100% tested. 9. ac specifcations are tested with input transition times less than 3ns, output reference levels of 1.5v (except tdis test), and input levels of nominally 0 to 3.0v. output loading may be a resistive divider which provides for specifed i oh and i ol at an output voltage of v oh min and v ol max respectively. alternatively, a diode bridge with upper and lower current sources of i oh and i ol respectively, and a balancing voltage of 1.5v may be used. parasitic capacitance is 30 pf minimum, and may be distributed. this device has high-speed outputs capable of large instantaneous current pulses and fast turn-on/turn-off times. as a result, care must be exercised in the testing of this device. the following measures are recommended: a. a 0.1 f ceramic capacitor should be installed between v cc and ground leads as close to the device under test (dut) as possible. similar capacitors should be installed between device v cc and the tester common, and device ground and tester common. b. ground and v cc supply planes must be brought directly to the dut socket or contactor fngers. c. input voltages on a test fxture should be adjusted to compensate for inductive ground and v cc noise to maintain required dut input levels relative to the dut ground pin. 10. each parameter is shown as a minimum or maximum value. input requirements are specifed from the point of view of the external system driving the chip. setup time, for example, is specifed as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. responses from the internal circuitry are specifed from the point of view of the device. output delay, for example, is specifed as a maximum since worst-case operation of any device always provides data within that time. n = total number of device outputs c = capacitive load per output v = supply voltage f = clock frequency notes devices incorporated ncv f 4 2
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 23 9/19/05 lds.3311-c video imaging products 11. for the t ena test, the transition is measured to the 1.5v crossing point with datasheet loads. for the t dis test, the transition is measured to the ?200mv level from the measured steady-state output voltage with ?10ma loads. the balancing voltage, v th , is set at 3.0 v for z-to-0 and 0-to-z tests, and set at 0 v for z-to-1 and 1-to-z tests. 12. these parameters are only tested at the high temperature extreme, which is the worst case for leakage current. notes figure a. output loading circuit figure b. threshold levels s1 i oh i ol v th c l dut devices incorporated oe 0.2 v t di s t en a 0.2 v 1.5 v 1 .5 v 3.0v vt h 1 z 0 z z 1 z 0 1.5 v 1.5 v 0v vt h v ol * v oh * v ol * v oh * measured v ol with i oh = C10ma and i ol = 10ma measured v oh with i oh = C10ma and i ol = 10ma
LF3311 horizontal / vertical digital image filter improved performance logic devices incorporated 24 9/19/05 lds.3311-c video imaging products package and ordering information 144-pin speed 9 ns LF3311qc9 9 ns LF3311qc9g (green) plastic quad flatpack (q5) 0c to 70c--commercial screening logic devices incorporated reserves the right to make corrections, modifcations, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. logic devices does not assume any liability arising out of the application or use of any product or circuit described herein. in no event shall any liability exceed the purchase price of logic devices products. logic devices products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with logic devices. furthermore, logic devices does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in signifcant injury to the user. devices incorporated vcc vcc gnd gnd hcen hca 0 hca 1 hca 2 hca 3 gnd vcc hca 4 hca 5 hca 6 hca 7 gnd vcc hcf 0 hcf 1 hcf 2 hcf 3 hcf 4 hcf 5 gnd vcc hcf 6 hcf 7 hcf 8 hcf 9 hcf 10 hcf 11 hld gnd gnd vcc vcc vcc gnd gnd hshen hacc hrsl 0 hrsl 1 hrsl 2 hrsl 3 gen gnd vcc dout 0 dout 1 dout 2 dout 3 dout 4 dout 5 dout 6 vcc gnd dout 7 dout 8 dout 9 dout 10 dout 11 gnd vcc vrsl 3 vrsl 2 vrsl 1 vrsl 0 vacc gnd gnd vcc vcc vcc gnd gnd txfr vshen vcen vca 7 vca 6 vca 5 vca 4 gnd vcc vca 3 vca 2 vca 1 vca 0 gnd vcc vb 11 vb 10 vb 9 vb 8 vb 7 vb 6 gnd vcc vb 5 vb 4 vb 3 vb 2 vb 1 vb 0 gnd gnd vcc vcc gnd di n 0 di n 1 di n 2 di n 3 di n 4 di n 5 vcc gnd di n 6 di n 7 di n 8 di n 9 di n 10 di n 11 vcc gnd vld vcf 0 vcf 1 vcf 2 vcf 3 vcf 4 vcf 5 vcc gnd vcf 6 vcf 7 vcf 8 vcf 9 vcf 10 vcf 11 clk gnd vcc 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 to p view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109

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